1. Field of the Invention
This invention relates in general to the fabrication of integrated-circuit (IC) devices, and more particularly to a method for fabricating polycide gate MOSFET devices that prevent problems of peeling and surface roughness of the polycide by performing an additional ion implantation step.
2. Description of the Prior Art
The current trend in VLSI design toward denser and more complex circuitry produces closely spaced and smaller geometries on larger chips, which result in narrower and longer interconnect lines. In the past, polysilicon was a satisfactory material for use as the gate electrodes and the interconnecting lines. However, as these geometries become smaller, polysilicon is too high in resistivity for these applications and it starts having too big of an impact on RC time delays and IR voltage drops. The use of a combination of refractory metal silicides with polysilicon, referred to as polycide, has proven suitable for VLSI fabrication because of its lower resistivity.
Silicides of certain refractory metals, e.g. tungsten, molybdenum, titanium, and tantalum have been proven to be suitable for use as a low resistance interconnect material for VLSI integrated circuit fabrication. These silicides pair very well with heavily doped polysilicon to form polycide gates. The preferred deposition technique for refractory metal silicides is by low pressure chemical vapor deposition (LPCVD). Tungsten silicide has particularly been found to be capable of overcoming some shortcomings, such as stoichiometry control, surface roughness, adhesion, oxidation and reproducibility to be very useful in combination with polysilicon.
The as-deposited tungsten disilicide has an amorphous structure (WSi.sub.x) and crystallizes into hexagonal tungsten disilicide (WSi.sub.2) when it is annealed around 450.degree. C. After annealing at temperatures higher than 650.degree. C., the hexagonal phase will transform into a tetragonal phase. During thermal treatment of a silicon wafer, such as is done in forming a layer of oxide, part of silicon in the tungsten disilicide precipitates at the disilicide/polysilicon interface or reacts with the oxygen ambient to form silicon dioxide. Therefore, a higher silicon concentration in the tungsten silicide is necessary to provide excess silicon during high temperature oxidation, to maintain tungsten silicide stoichiometry, and to improve silicide adhesion to the polysilicon layer.
However, it is also a fact that peeling of this polycide film frequently occurs after a thermal treatment. This, in turn, causes the yield of the product to decrease. With reference to FIGS. 1a to 1f, the process steps of a prior art MOSFET device having a polycide gate is now described.
Referring to FIG. 1a, there is shown a semiconductor substrate 10, such as a p type monocrystalline silicon substrate. A gate oxide layer 12 with thickness between 100 .ANG. to 400 .ANG., and preferably such as 250 .ANG., is formed over the semiconductor substrate 10, preferably by thermal oxidation. A polysilicon layer 14 with thickness of between 1000 .ANG. to 4000 .ANG., and preferably such as 2000 .ANG., is formed over the gate oxide layer 12 preferably by deposition, such as by LPCVD. The polysilicon layer 14 is implanted with phosphorous ions with a dosage over 1.times.10.sup.15 atoms/cm.sup.2 so as to provide a sufficient concentration of carriers. The resulting surface is then cleaned by dipping in a dilute HF solution. An amorphous tungsten silicide layer 16 with thickness of between 500 .ANG. to 4000 .ANG., and preferably such as 2500 .ANG., is formed over the polysilicon layer 14 preferably by LPCVD.
Turning now to FIG. 1b, a photoresist layer (not shown) is coated and patterned on the tungsten silicide layer 16 by a conventional lithography process. Portions of the tungsten silicide layer 16 and the polysilicon layer 14 not covered by the photoresist layer are removed by anisotropic etching, such as by reactive ion etching (RIE), to define a gate electrode structure. The photoresist layer is then removed by an appropriate solvent.
Referring to FIG. 1c, a first thin oxide layer 18 with thickness of between 300 .ANG. to 500 .ANG. is formed over the exposed surfaces of the gate oxide layer 12, the polysilicon layer 14, the tungsten silicide layer 16, and the semiconductor substrate 10 by thermal oxidation. Meanwhile, the tungsten silicide layer 16 is transformed from the amorphous form into a crystalline form (i.e. WSi.sub.x .fwdarw.WSi.sub.2). Next, by using the gate electrode structure as a mask, n type impurities, such as phosphorous ions with an energy preferably between 30 to 70 KeV and with dose preferably between 1.times.10.sup.12 to 1.times.10.sup.14 atoms/cm.sup.2, are implanted into the semiconductor substrate 10 to form n.sup.- lightly doped source/drain regions 13.
Please now turn to FIG. 1d. An oxide layer 20 with thickness of between 1000 .ANG. to 4000 .ANG., and preferably such as 2400 .ANG., is formed over the first thin oxide layer 18 preferably by CVD. The oxide layer 20 is densified in nitrogen ambient at temperature of about 900.degree. C. Then, the oxide layer 20 and the first thin oxide layer 18 are anisotropically etched back, such as by RIE, to form sidewall spacers 20 on the side walls of the gate electrode structure, as is shown in FIG. 1e.
Referring to FIG. 1f, a second thin oxide layer 22 with thickness of between 300 .ANG. to 500 .ANG. is formed over the exposed surfaces of the gate electrode structure, and the semiconductor substrate 10 by thermal oxidation. Peeling of the tungsten silicide 16 is apt to occur after this thermal treatment and the tungsten silicide layer 16 is shown having peeled away from polysilicon layer 14 in this figure. As a result of this peeling, increasing particles and decreasing yield.
There are mainly two steps which cause the tungsten silicide to peel. First, the tungsten silicide layer 16 is damaged by the previous etching process, such as sidewall spacer etching, resulting in less content of silicon in tungsten silicide. Second, after the thermal treatment, the tungsten silicide layer 16 transforms from its amorphous form into a crystalline which increases the stress in layer 16 and the added stress adversely affects the layer's adhesion properties.
In order to avoid the etching damage, a prior art method has been proposed which applies a barrier cap layer 30, such as a polysilicon layer, over the tungsten silicide layer 16, as is shown in FIG. 2. However, after defining the gate electrode structure by RIE, sidewall portions of the tungsten silicide layer 16 are exposed. When a thin oxide layer is formed by a thermal treatment, the exposed portions of the tungsten silicide layer 16 will roughen at its exposed surface, which is referred to as "popcorn phenomenon", resulting particle contamination and device failure.